1. Field of the Invention
The present invention relates generally to integrated circuits, and more specifically to a magnitude comparator circuit.
2. Description of the Prior Art:
Magnitude comparator circuits are used when it is necessary to determine the relationship between the magnitude of two numbers--whether a number is equal to, less than, or greater than another number in magnitude. Such circuits find a wide variety of uses in the electronics industry. For example, magnitude comparators are used in conjunction with subtractors to generate high speed flag logic for FIFO (First In First Out) memories. Magnitude comparator circuits are also used in arithmetic logic units (ALU's) found in personal computers (PCs) and other computers and by microprocessors for the execution of certain instructions.
Serial magnitude comparators are a common form of comparator circuits in the prior art. They have a number of individual bit comparators that together serially determine the magnitude of a number relative to another number. First, the least significant bits (LSBs) of the two numbers are compared before comparing the next bits, the LSB+1. This process continues serially until the most significant bits (MSBs) have been compared. The serial process can be quite consuming; at least 16 gate delays will be incurred for comparing two 16 bit words.
The bit comparators which comprise a serial magnitude comparator have a total of four inputs: an input equal to a bit from a fixed value, an input equal to a bit from a binary number being compared to the fixed value, an input equal to the complement of the binary number to be compared, and an input from the compare output of the previous bit comparator. The parallel magnitude comparator compares the binary number input to the fixed value input to determine the magnitude of the binary number relative to the magnitude to the fixed value.
The compare output of a bit comparator is input to the subsequent bit comparator and reflects whether the binary value is equal to, less than, or greater than the magnitude of the fixed value. If the fixed value input is greater than the binary value input, then the compare output is a logic high. If, however, the fixed value input is less than or equal to the binary value input, then the compare output is a logic low. This comparison process starts with the least significant bit (LSB) comparator and continues until the most significant bit (MSB) comparator finishes its comparison operation. The bit comparator with the highest order bit of difference determines the state of the final compare output.
The gate delays associated with serial magnitude comparators can have an adverse effect on overall system performance. In FIFO (First In First Out) memory applications, a magnitude comparator is often used in conjunction with a subtractor circuit to generate FIFO flag logic. In magnitude comparators where a binary number is being compared to a fixed value, the fixed value often serves as a programming value for setting the FIFO flag to a certain level. A FIFO flag tells the user how full the FIFO is. Flag logic, which is dependent on the comparator and subtractor, must be generated quickly. If the magnitude comparator is slow, it will have an adverse affect on how quickly flag logic may be generated and overall FIFO performance will suffer. A fundamental way to enhance the speed at which FIFO flag logic is generated is to minimize propagation and gate delays associated with serial magnitude comparators. It would be desirable to accomplish this using current magnitude comparator design.